RISCV32I Pipelined Processor + UVM testbench

As an undergraduate, I loved to design RISC-V processors and deploy them on FPGAs. Now, as a master’s student, I built another RISCV-32I 5-stage pipelined core, but this time using Chisel HDL. I also went beyond the RTL design and built a complete UVM-based verification environment as well.

I was able to verify the functionality of the core using the riscv-tests.

I started this work as the class project of “Architecture of Digital Systems I (ADS1)” module at RPTU. Initially it was a simplified processor supporting only arithmetic and logic operations. Since I was passionate about the project, I continued working on it after completing the module, adding the remaining control-flow instructions and pipeline hazard handling to turn it into a complete RV32I 5-stage pipelined processor.

Following suggestions from M.Sc. Tobias Jauch, I also developed a complete UVM-based testbench to verify the processor.

Now this processor design and its UVM testbench are being used as the class project for ADS1 module at RPTU. It is great to see my work being used to give students hands on experience with RISC-V architecture and UVM verification.

I would like to thank M.Sc. Tobias Jauch for supervising and supporting me throughout the project, and Prof. Dr.-Ing. Wolfgang Kunz for teaching us and for his continuous support and inspiration throughout my master’s studies.

If you are interested in the design, you can check out the project here: link